The invention relates to a phase-locked loop, comprising:
an oscillator intended to produce an output signal having an oscillation frequency whose value depends on that of a tuning signal,
a frequency divider intended to receive the output signal from the oscillator and to supply an output signal having a frequency which is R times lower than the oscillation frequency, and
a phase/frequency detector intended to compare the frequency of the output signal of the divider with a so-called comparison frequency of a comparison signal, and to supply the tunning signal, whose value is representative of the result of the comparison, to the oscillator.
Such a phase-locked loop is described in European patent application EP 0 821 488 A1. In the majority of known phase-locked loops, the frequency divider receives the output signal from the oscillator and supplies an output signal having a frequency that is N times lower than the oscillation frequency to a phase/frequency comparator, N being an integer whose value is equal to that of a control word. The phase/frequency comparator compares this frequency with a so-called comparison frequency of a comparison signal originating, for example, from a quartz oscillator. If the output frequency of the frequency divider is below the comparison frequency, the phase/frequency comparator commands an increase of the oscillation frequency until the oscillation frequency is equal to N times the comparison frequency. Since the value of the comparison frequency is fixed, the choice of the value of N for the nominal word determines the value of the oscillation frequency. Consequently, the minimum interval between two oscillation frequency values is equal to the value of the comparison frequency. It has been found that the performance in terms of noise of a phase-locked loop is better as the comparison frequency is higher. However, choosing a high comparison frequency means an increase of the minimum interval between two values of the oscillation frequency, which interval is determined by the conditions wherein the phase-locked loop is employed. Thus, in applications where the output signal of the oscillator is used to receive hertzian digital television signals, this minimum interval is predetermined and set at 166.67 kHz by the OFDM standard.
To maintain a constant minimum interval while increasing the value of the comparison frequency, it is thus necessary to use a frequency divider whose division ratio has a non-integer value. Such frequency dividers are commonly referred to as xe2x80x9cfractional-Nxe2x80x9d frequency dividers. Their division ratio is determined by at least two parameters.
For a large number of known fractional-N type dividers, the division ratio R can be expressed as follows: R=N+k/q, where N and k are first and second integer parameters, and q is a third integer parameter whose value is predetermined by the value of the minimum interval between two oscillation frequencies, which is to be kept constant. Thus, q=FCOMP/FSTEP, where FCOMP is the chosen comparison frequency and FSTEP is the minimum interval. Such frequency dividers carry out a division by N during qxe2x88x92k operating cycles of the phase-locked loop, an operating cycle corresponding to one period of the output signal of the frequency divider, and subsequently a division by N+1 during k operating cycles of said loop. Thus, the average division ratio of q cycles of the phase-locked loop is equal to N+k/q.
An balanced operating mode of the phase-locked loop is defined as being a mode wherein the following relation is verified: FDIV=FLO/R=FCOMP, where FDIV is the frequency of the output signal of the frequency divider, and FLO and FCOMP are, respectively, the oscillation and comparison frequencies.
This means that, at the close of q operating cycles of the phase-locked loop, the output signal of the frequency divider and the comparison signal must be in phase and have equal frequencies, i.e. at the close of q operating cycles, in principle, no correction should be made in the value of the oscillation frequency. However, in practice it has been found that at the close of each cycle wherein the division ratio of the frequency divider is equal to N, the output signal of the frequency divider presents a phase shift with respect to the comparison signal, since its frequency FDIV is slightly higher than the comparison frequency FCOMP, FDIV being equal to FLO/N, while FCOMP=FLO/(N+k/q). Although such phase shifts are theoretically compensated for during the cycles wherein the division ratio of the frequency divider is equal to N+1, in practice each phase shift is detected by the phase/frequency detector, which automatically causes a useless and untimely correction of the value of the oscillation frequency. Such corrections generate a parasitic phase modulation of the output signal of the oscillator around its central oscillation frequency, i.e. the instantaneous value of the oscillation frequency varies during the balanced operating mode.
However, the main function of a phase-locked loop is to generate a signal which has an accurately defined oscillation frequency and is intended to be used as a reference, for example by frequency converters included in tuners intended to receive radioelectric signals, inside television receivers or radiotelephones, among other possible applications. A signal affected by a parasitic phase modulation is illesuited for such a purpose.
It is an object of the invention to substantially overcome this drawback by providing a phase-locked loop having a good noise performance by virtue of the use of a fractional-N frequency divider, without said divider introducing a parasitic phase modulation into the output signal of the oscillator whose oscillation frequency is regulated by the loop.
Indeed, in accordance with the invention, a phase-locked loop in accordance with the opening paragraph is provided with correction means intended to detect a parasitic phase modulation applied to the output signal of the oscillator, and to apply a phase modulation, which is similar to said parasitic phase modulation, to the comparison signal.
In the phase-locked loop in accordance with the invention, the input signals of the phase/frequency detector are made synchronous during the balanced operating mode. Consequently, the phase/frequency detector does not cause untimely corrections, thereby causing the parasitic phase modulation of the output signal of the oscillator to disappear. It is to be noted, in addition, that the invention enables the parasitic modulation to be automatically eliminated inside the phase-locked loop without any outside intervention.
In a particular embodiment of the invention, the correction means include:
storage means for storing the value adopted by the tuning signal at the close of q cycles of the phase-locked loop, and
phase-shifting means for applying a phase shift to the comparison signal at each ith (i=1 to q) cycle of the phase-locked loop, the value of said phase shift being determined by the product of the value stored by the storage means and a coefficient L(i) that is specific to the cycle in question.
In this embodiment, a non-zero value of the tuning signal at the close of q operating cycles of said loop signals the existence of a parasitic phase modulation of the output signal of the oscillator. The value of this tuning signal determines the magnitude of the phase shifts to be imposed on the comparison signal so as to cause this comparison signal to be affected by a phase modulation which is identical to the parasitic phase modulation. In the course of time, the magnitude of the parasitic modulation decreases, due to the correction thus effected, which implies a gradual reduction of the value stored by the storage means and hence an automatic reduction of the magnitude of the corrections made in the phase of the comparison signal, said automatic reduction being attributable to the particular nature of the phase-shift means described hereinabove. When the value becomes zero, no correction is applied to the comparison signal anymore.
The phase-shift means described hereinabove enable the comparison signal to be subjected, in the course of each operating cycle of the phase-locked loop, to a phase shift such that the comparison signal thus obtained and the output signal of the frequency divider are in phase at the close of this cycle, irrespective of the value of the division ratio in the course of this cycle. Indeed, the value of the coefficient L(i) is determined for each cycle, taking into account the division ratio used in the course of said cycle. The values of the coefficients L(i) are advantageously chosen by means of the following relations:
L(i)=L(ixe2x88x921)+k, if L(ixe2x88x921) less than q,
and
L(i)=L(ixe2x88x921)xe2x88x92q, if L(ixe2x88x921) greater than q.
Many embodiments of the phase-shift means can be envisaged and are within the reach of those skilled in the art. A particularly advantageous embodiment takes advantage of the fact that the comparison signal, originating most usually from a quartz oscillator having well-defined characteristics, shows a linear course proximate to the zero value, the zero-crossings of the comparison signal being occurrences with respect to which edges of the output signal of the frequency divider are compared.
A voltage shift of the comparison signal then causes a time shift of said zero-crossings, the value of said shift being proportional to that of the voltage shift. In this embodiment of the invention, the phase-shift means will thus be advantageously designed to apply a voltage shift to the comparison signal in the course of each ith (i=i to q) cycle of the loop, the size of said voltage shift being proportional to L(i) times the value stored by the storage means.
As described hereinabove, phase-locked loops using a fractional-N frequency divider are advantageously employed to generate reference signals enabling frequency conversions, while yielding a good noise performance, in certain applications where the minimum interval separating two oscillation frequencies has a set value. In an application of such phase-locked loops, the invention thus relates to a device intended to receive radioelectric signals, for example a television receiver or a radiotelephone, including:
an input stage intended to receive a radioelectric signal and to convert this signal to an electronic output signal having a so-called radio frequency,
a phase-locked loop as claimed in claim 1, intended to adjust the oscillation frequency of the output signal of an oscillator, and
a mixer intended to receive the output signals from the input stage and the oscillator, and to supply a signal whose frequency is equal to the difference between the radio frequency and the oscillation frequency.
These and other aspects of the invention will be apparent from and elucidated with reference to the non-limitative embodiments(s) described hereinafter.